Capacitive Transimpedance Amplifiers (CTIAs) are frequently used in various arrangements to amplify the output of a photodiode, or other detector, to a usable voltage within a read-out integrated circuit unit cell of a focal plane array. A typical focal plane array includes a two-dimensional array of detector elements, or pixels (i.e., unit cells), organized by rows or columns. CTIAs provide a low impedance to the photodiode and isolate the photodiode from the output voltage of an operational amplifier in the CTIA. A feedback capacitor within a feedback loop of the CTIA is generally used to improve the stability of the CTIA. Conventional imaging circuits generally also include a Correlated Double Sampling (CDS) capacitor and employ CDS schemes to improve noise performance. CDS is a method of noise reduction in imaging circuits in which a reference voltage of a pixel is removed from a signal voltage of the pixel at the end of each integration period.
Existing schemes for imaging circuitry often utilize a CTIA architecture and CDS techniques in combination with sample-hold circuitry. For instance, many conventional read-out integrated circuit unit cells include CTIA and CDS architecture for processing a charge generated by a photodiode corresponding to the flux of light of various wavelengths at that photodiode. Often the charge is accumulated at a capacitor within the circuit, which effectively integrates the charge to produce an output voltage. The output voltage corresponds to the intensity of the flux over a given time interval, generally referred to as the integration interval. Such circuits generally convey the output voltage to downstream components and reset the voltage of the capacitor to a reset value. For instance, the output voltage may be sampled and held at a sample-hold capacitor and periodically bled and digitized by circuitry associated with the unit cell to generate one or more binary values.